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Features
* * * * * * * * * * * * *
Supply Voltage up to 40 V Operation Voltage up to 16.5 V RDS ON Typically 1 W at 27C, Maximum 2.0 W at TJ = 150C Up to 1.3 A Output Current Two Half-bridge Outputs Formed by Two High-side and Two Low-side Drivers Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors Very Low Quiescent Current IVS < 1 A in Standby Mode Outputs Short-circuit Protected Overtemperature Protection Overvoltage Protection for Supply Voltage up to 40 V Outputs Withstand DC Voltages up to 40 V Diagnosis Function for Overtemperature and Overvoltage at the Power Supply SO20 Power Package
Dual Half-bridge DMOS Output Driver ATA6822 Preliminary
Description
The ATA6822 is a fully protected driver interface designed in 0.8 m BCDMOS technology. It is used to control different loads by setting two logic level input signals. The ATA6822 can be configured to cover a wide range of automotive and industrial applications. Each of the push-pull output stages is capable to drive currents up to 1.3 A. The drivers are connected internally to form two half-bridges and can be controlled separately with two logic level input signals. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design supports the application as a DC motor driver especially. Protection is guaranteed in terms of short-circuit conditions, overtemperature and overvoltage up to 40 V supply voltage. A diagnosis function in case of overtemperature and overvoltage is embedded. To reduce the overall current consumption the ATA6822 can be switched into standby mode. The output pins are designed to withstand DC voltages up to 40 V. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for demanding up-market applications. Figure 1. Block Diagram
DIAG
11 10 12 9
EN IN1 IN2
Control logic
OV protection
1
Vs
Charge pump
4 GND
NC NC NC NC NC
3 8
5 GND 6 7 GND GND GND
13 14 18 20
Thermal protection
15 GND 16 17 2 OUT2 19 OUT1 GND GND
Rev. 4565A-BCD-09/02
1
Pin Configuration
Figure 2. Pinning SO20
N.C. OUT1 N.C. GND GND GND GND N.C. IN1 DIAG
20
19
18
17
16
15
14
13
12
11
Chip Leadframe
1 2 3 4 5 6 7 8 9 10
VS
OUT2
N.C.
GND
GND
GND
GND
N.C.
IN2
EN
Pin Description
Pin 1 2 Symbol VS OUT2 Function Power supply for output stages OUT1, OUT2 and internal supply. Push-pull power output formed by internal high-side switch and low-side switch with internal reverse diodes, short circuit protection, overtemperature protection, diagnosis function for overtemperature and overvoltage. Not connected. Ground, reference potential for signal and power, internal connected to pin 5, 6, 7, 14, 15, 16 and 17 by lead frame. Ground, see Pin 4. Ground, see Pin 4. Ground, see Pin 4. Ground, see Pin 4. Schmitt trigger input with hysteresis to control the outputs OUT1 and OUT2. Schmitt trigger input with hysteresis to switch the IC into standby and outputs into tristate condition. Diagnosis open drain output, reports overvoltage or overtemperature detection. Schmitt trigger input with hysteresis to control the outputs OUT1 and OUT2. Not connected. Ground, see Pin 4. Ground, see Pin 4. Ground, see Pin 4. Ground, see Pin 4. Not connected. Push-pull power output, see Pin 2. Not connected.
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
N.C. GND GND GND GND N.C. IN2 EN DIAG IN1 N.C. GND GND GND GND N.C. OUT1 N.C.
2
ATA6822
4565A-BCD-09/02
ATA6822
Table 1. Functional Overview
IN1 --High High Low Low --IN2 --High Low High Low --EN Low High High High High High OUT1 Tristate Source Source Sink Sink Tristate OUT2 Tristate Source Sink Source Sink Tristate DIAG - Level High High High High High Low Overvoltage and overtemperature detected Note Standby mode Recommended mode for braking DC motors
Functional Description Output Stages
The basic function is shown in Table 1. Each of the two output stages, OUT1 and OUT2, can be controlled separately via the logic level input signals, IN1 and IN2. The logic level enable input signal, EN, switches the IC into standby mode reducing overall current consumption to less than 1 A. Each of the output stages is capable to drive load currents up to 1.3 A. Depending on the combination of the input signals, IN1 and IN2, different modes for the output stages can be selected, see . The output OUT1 as well as output OUT2 can be either switched as current source or as current sink. The outputs are designed to withstand DC voltages up to 40 V. The ON resistance (RDS ON) of each output stage is 1 W at 27C junction temperature. For worst case calculations a maximum ON resistance (RDS ON) of 2 W needs to be considered. In DC motor applications the best case for braking is the Source/Source mode, see Table 1. For braking the sink, the driver stage has to be switched into Source mode. Now, the inductive current has a low resistance path to battery voltage, thus the internal IC power dissipation is reduced.
No Shoot-through Condition No Leakage Current Condition
An active high side switch off-circuitry prevents shoot-through current, while the output switches are in transition from Source to Sink state or vice versa. Therefore, it is guaranteed that the HS stages are switched off before the LS stages can be activated. In failure mode, like overtemperature and overvoltage, if the high side switch-off circuitry is still activated, a load connected to battery could draw a leakage current from battery to ground. To get a tristate mode as described in Table 1, the high side switch-off circuitry is disabled during failure mode. An implemented diagnosis function detects overtemperature and overvoltage conditions. The output, DIAG, is designed as open collector output with an pull up resistor connected externally. The DIAG output current is limited internally. The circuit features an overvoltage disable function by monitoring the supply voltage VVS. The overvoltage protection circuitry disables both, the low side as well as the high side output stage, if supply voltage exceeds the voltage threshold 19.5 V. The overvoltage sense comparator provides a hysteresis of 0.9 V. Both outputs are switched into tristate in overvoltage condition and the diagnostic output will be switched on. With a pull up resistor connected to 5 V externally, the output voltage at Pin 11 (DIAG) switches below 0.5 V.
Diagnosis
Overvoltage Protection
3
4565A-BCD-09/02
Overtemperature Protection
The thermal shutdown protection circuitry switches off the outputs (tristate) and activate the diagnostic output, if junction temperature exceeds the thermal switch-off threshold temperature of 175C. In tristate mode the output drivers cool down and if the junction temperature falls below the thermal switch on threshold the outputs switch back into normal operation. The IC is designed with a thermal hysteresis of 15 Kelvin between switch off and switch on state. Depending on the thermal environment of the IC a thermal oscillation has to be considered during output switch-off, cool down and switch-on state. The output currents are sensed by a short current protection circuitry and are limited to a maximum short circuit current of approximately 1.7 A.
Short Circuit Protection
Absolute Maximum Ratings
All values refer to GND pins.
Parameters Supply voltage Logic input voltage Logic output voltage Input current Output short-circuit current -0.3 V < VOUT < VVS +0.3 V DC sink current -0.3 V < VDIAG < 7 V Reverse conducting current (tpulse = 150 s) Junction temperature range Storage temperature range Pin 1 9, 10, 12 11 9, 12 2, 19 11 2, 19 towards Pin 1 Symbol VVS VEN, VIN1,2 VDIAG IIN1,2 IOUT1,2 IDIAG IOut1,2 TJ TSTG Value -0.3 to +40 -0.3 to +7 -0.3 to +7 -10 to +10 Internally limited Internally limited 17 -40 to +150 -55 to +150 A C C Unit V V V mA
Thermal Resistance
Parameters Junction pin Junction ambient Note: 1. Depend on cooling area on PCB Test Conditions/Pins Measured to GND: 4 to 7, 14 to 17 Symbol RthJP RthJA Value 15 50
(1)
Unit K/W K/W
Operating Range
Parameters Supply voltage Logic input voltage Junction temperature range Note: 1. Threshold for qvervoltage detection Test Conditions/ Pins 1 9, 10, 12 Symbol VVS VEN, VIN1, 2 TJ Min. 7 -0.3 -40 Typ. Max. V_ovth 7 150
(1)
Unit V V C
4
ATA6822
4565A-BCD-09/02
ATA6822
Noise and Surge Immunity
Parameters Conduted interference Interference suppression ESD (Human Body Model) ESD (Machine Model) Note: 1. Test pulse 5 maximum voltage 40 V (load dump) Test Conditions ISO 7637-1 VDE 0879 part 2 ESD S 5.1 JEDEC A115A Value Level 4 (1) Level 5 2 kV 200 V
Electrical Characteristics
7 V < VVS < 16.5 V, -40C < TJ < 150C, EN = HIGH, unless otherwise specified, all values refer to GND pins.
No. 1 1.1 1.3 2 2.1 2.2 3 3.1 3.2 3.3 4 4.1 Parameters Quiescent current (at VS) Supply current (at VS) Supply overvoltage threshold Supply overvoltage hysteresis Thermal Shutdown Thermal shutdown Thermal shutdown Thermal shutdown hysteresis Output Specification (OUT1, OUT2) ON resistance to VS or GND Source overcurrent limitation and shutdown threshold Sink overcurrent limitation and shutdown threshold Leakage current 4.4 VEN = 0 V, no load connected Low side: VVS = VOUT1 = VOUT2 = 40 V High side: VVS = 16.5 V, VOUT1 = VOUT2 = 0 V 2, 19 2, 19 RDS ON1, 2 IOUT 1, 2 -2.2 1 -1.7 2 -1.3 W A A A 9 9 9 TJ_switch off TJ_switch on DTJ_switch 150 135 175 160 15 200 185 C C K B B B Test Conditions VEN = 0 V, VVS < 16.5 V EN = 5 V, IOUT1 = IOUT2 = 0 A Pin 1 1 Symbol IVS IVS Min. -1 Typ. Max. 5 5.5 Unit A mA Type (*) A A Current Consumption
Overvoltage Shutdown 1, 11 1, 11 Vovth Vovth_hys 17.5 0.9 20.5 V V A A
4.2
2, 19
IOUT 1, 2
1.3
1.7
2.2
A
A
4.3
2, 19
IOUT_leak
-5
5
A
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
5
4565A-BCD-09/02
Electrical Characteristics (Continued)
7 V < VVS < 16.5 V, -40C < TJ < 150C, EN = HIGH, unless otherwise specified, all values refer to GND pins.
No. 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 6.1 Parameters Turn on delay time Turn on delay time Turn off delay time Turn off delay time Turn on HS delay time Turn off LS delay time Turn off HS delay time Turn on LS delay time Logic Inputs (EN, IN1, IN2) Low enable voltage High enable voltage Hysteresis of enable voltage Enable input current Low input voltage High input voltage Hysteresis of input voltage Input bias current Pull-down current Logic Output (DIAG) Diagnostic output drop IDIAG = 0.5 mA, overvoltage or overtemperature 11 VDIAG 0.5 V A VIN = 0 V, VEN = 5 V VIN = 5 V, VEN = 5 V VEN = 5 V 10 10 10 10 9, 12 9, 12 9, 12 9, 12 9, 12 VENL VENH DVEN 1, 2 IEN VIN1, 2L VIN1, 2H DVIN1, 2 IIN1, 2 IIN1, 2 3.5 200 -1 0 35 600 1 50 3.5 200 90 600 200 2 2 V V mV A V V mV A A A A A A A A A A A Test Conditions See Figure 3 and Figure 4 VVS = 13 V, measured with 93 W to GND for high-side and 93 W to VS for low-side Pin 2, 19 2, 19 2, 19 2, 19 2, 19 2, 19 2, 19 2, 19 Symbol tONLH_HS tONLH_LS tOFFHL_HS tOFFLH_LS tdLH_HS tdLH_LS tdHL_HS tdHL_LS Min. Typ. 50 50 Max. 80 80 10 1.5 10 1.5 5 15 Unit s s s s s s s s Type (*) A A A A A A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
6
ATA6822
4565A-BCD-09/02
ATA6822
Figure 3. Timing Diagram
OUT1: SRC OUT2: SRC OUT1: SNK OUT2: SRC OUT1: SNK OUT2: SNK OUT1: SRC OUT2: SNK
Standby
Standby
ENABLE
IN 1
IN 2
tONHL_LS
OUT 1
tdLH_LS
tdHL_LS
tOFFLH_LS
OUT 2
tONLH_HS
tdHL_HS
tdLH_HS
tOFFHL_HS
7
4565A-BCD-09/02
Figure 4. Test Circuit
Vcc
IN1 IN2
12 9
logic
Charge pump
4 GND
CS
V_EN
NC
V_IN 1 V_IN 2
3 8
5 GND 6 7 GND GND GND
NC NC NC NC
13 14 18 20
Thermal protection
15 GND 16 17 2 OUT2 19 OUT1 GND GND
R_Load 93R
R_Load 93R
Figure 5. Application Circuit
Vcc
12 9
logic
Charge pump
4 GND
CS
IN2
C C
NC NC NC NC NC
3 8
5 GND 6 7 GND GND GND
13 14 18 20
Thermal protection
15 GND 16 17 2 OUT2 19 OUT1 GND GND
8
ATA6822
4565A-BCD-09/02
+
+
Vcc 5V
47k Vs
DIAG
11 10
EN IN1
Control
OV protection
1
V s
D1 VBAT D2
+
+
Vcc 5V
47k Vs
DIAG
11 10
EN
Control
OV protection
1
V s
D1 VBAT
D2
ATA6822
Application Notes
It is strongly recommended to connect the blocking capacitors at VS as close as possible to the power supply and GND pins, see Figure 5. Recommended values for capacitors at VS, electrolytic capacitor C = 22 F in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOUT (see Absolute Maximum Ratings). To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins.
Ordering Information
Extended Type Number ATA6822 Package SO20 Remarks -
Package Information
Package SO20
Dimensions in mm
12.95 12.70 9.15 8.65 7.5 7.3
2.35 0.25 10.50 10.20 11
0.4 1.27 11.43 20
0.25 0.10
technical drawings according to DIN specifications
1
10
9
4565A-BCD-09/02
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4565A-BCD-09/02 xM

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